To apply digital signal processing to real-world data, it is often necessary to convert an analog signal into a digital format. To insure reasonable fidelity in this conversion, it is desirable to sample the analog signal at a rate substantially greater than bandwidth of the analog signal. These sampled signal values are then converted sample by sample at high speed into their equivalent digital values represented by "N" number of binary bits. Prior art ADCs, which typically use bipolar transistors, are able to operate at high rates (e.g., 50 MHz) and with 12-bit resolution. These ADCs require relatively large amounts of electrical power and are very costly. On the other hand, attempts to implement high speed, multi-bit ADCs with MOS technology have not been as successful as desired. Either cost was high because of poor chip yield or performance was substantially less than could be obtained using bipolar transistor technology.
A prior ADC, termed an "N-flash" ADC, simultaneously produces "N" data bits in parallel from a sampled analog voltage. The ADC comprises 2.sup.N -1 comparators which are closely matched to each other with each capable of high resolution. The ADC circuit momentarily connects all of these comparators at once to an analog input sampling circuit. A decoder circuit coupled to all of the comparators then determines the values of the N bits corresponding to the analog value of the input signal being sampled at that instant. An advantage of this type of ADC is the high speed at which it can operate. An important disadvantage is relatively low impedance load (and corresponding large switching transients) caused by connecting all of the comparators to the input circuit at the same time. As an example, a 12 bit flash ADC uses 4095 comparators.
Another type of ADC is a successive approximation device. This type of ADC, in its simplest form, calculates an output digital value from a sampled analog potential one bit at a time, from the most significant bit to the least significant bit. As each bit of the output value is generated, the partial digital value is converted to an analog value by an internal digital to analog converter (DAC), and the analog value is subtracted from the original sample value. This difference value is then used to generate the next less significant bit of the digital output value. In this form, at least N comparison operations are needed to produce an N-bit digital value.
In a more complex form, this type of ADC employs N or more successive approximation stages in parallel, each operating on a respectively different staggered clocking phase. In this configuration, one N-bit digital output value is produced for each clock cycle. An exemplary successive approximation ADC is described in my earlier U.S. Pat. No. 5,272,481 entitled ANALOG TO DIGITAL CONVERTER which is hereby incorporated by reference for its teachings on successive approximation ADCs.
One problem with any type of ADC implemented in MOS technology is linearity in the impedance of the sampling circuit. Sampling circuits for ADCs typically include a transmission gate which is turned on to charge a sampling capacitance to the instantaneous potential of the analog input signal and turned off to hold the charge level on the sampling capacitance.
A transmission gate is typically implemented as a PMOS transistor and an NMOS transistor having common source and drain connections. Complementary control potentials are applied to the gate electrodes of the PMOS and NMOS devices such that, when both devices are turned on, a conductive path exists for the signal being transmitted regardless of the instantaneous signal voltage. As is well known, there is a threshold gate to source voltage (V.sub.GS) below which MOS transistors do not conduct. When V.sub.GS is well above the threshold voltage, the transistor exhibits a linear impedance. When, however, V.sub.GS is close to the threshold voltage, the transistor exhibits a nonlinear impedance. By carefully selecting the size ratio between the NMOS and PMOS devices, the total impedance due to the parallel combination of the two devices can be made relatively constant when both devices are above their threshold voltages. This constant impedance, however, is generally restricted to a relatively small range. For signals outside of this range, the paired devices may exhibit nonlinear impedance. This nonlinear impedance may produce harmonic distortion in the signal that is being passed by the transmission gate.